1. 2 Bit Counter Vhdl
2. Program Counter Vhdl Xilinx
3. Vhdl Counter Code

Just wondering if I'm implementing a finite state machine in VHDL whether or not I need to state what all of the outputs are in every possible state? Even if I know that some outputs won't change from one state to the other and I know that the order of the states will also be in the same order?

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• Implement a decade-counter using VHDL; About Active-HDL. To start working with the program go to the Start -> All Programs -> Aldec program group and click the Active-HDL. I am trying to implement a 1-2-3-4-6 counter in VHDL but the count is incrementing form 1-7.

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For example, in this (forced) example:

From my understanding if I don't do this then latches are created?

It's not a big deal in something like that example but if I have a machine with more than 10 outputs and more than 10 states then my VHDL files start to look incredibly messy and I'm sure it must be bad practice to copy and paste the same thing over and over. Is there a better way of doing this?

edit: Can I define a 'default' state for an ouput? IE set b to be 1 outside of all the processes and then only define what it is in the case statements where it is 0? Would that work?

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Nick Larsen♦SamSam

4 Answers

Yes, you will infer latches if you only drive signals intended to be combinatorial in some branches of the process.

However, you can define a 'default' state for the signal simply by assigning a value to it before the case statement (but within the same process). For example:

Tomi JunnilaTomi Junnila

Three problems with your example code:

The last port in your port list should not have a semicolon:

In your register process, you should not have an 'else' statement. While this will probably be accepted by the tools, it will confuse your fellow-VHDL designers.

In your combinational logic, the sensitivity list should contain all signals that you read: process(a, currentstate). In this particular case (again) things will probably work out fine, but you are bound to infer latches or cause other problems if your sensitivity list is not correct.

As for your question:

1. Yes, you need to assign a value (for each state) to each signal in the combinational process.
2. As Tomi mentions, you can easily do this by assigning a default value in the beginning of the process.
3. But you can also write the entire state machine in one single synchronous process. This way, you do not have to assign a value to every signal in every state.

Just a note to Philippe's response (can't comment on it directly?).

I do prefer to write state machines in the two process style. It makes it very clear where you expect inferred flipflops and where you don't. It's also a bit more along the lines ofdescribing the hardware - imagine building a state machine with board level logic for example. Don ho greatest hits rar. The registered device matches the state <= next_state process,and the case statement maps to the and/or array in front of the state register.

Having said that, I typically use one process state machines for small simple tasks, and move over to two process machines for bigger ones. I will even sometimes use a third process for organizing state outputs into different 'task' groups. but not often. A really large state machine tends to tell me the architecture needs work.

Hi

the above process is problematic but not due to the sensitivity list. It is ok to only declare clk for sequential process. Both simulation and synthesis tools won't have problems with it. clk is the fastest changing/transitioning signal after all in your code.

However, you should use an (preferrably) asynchronous reset. Of course, vendors nowadays say that for FPGA design, resets are not even necessary; they happen at boot time. Or they propose a synchronous reset.

Still, an asynchronous reset is valuable for a board-based environment.

In short: add a reset to your design and fix its behavior properly.

Kind regardsNikolaos Kavvadias

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Term project for ECEC 355.

Usage

1. Download all the .vhd files here and add them to a project in modelsim.
2. Place binary mips instructions in a file instructions.txt and place it in the same directory as these .vhd files. The mips compiler will read the binary instructions from this file and run it after the first clock cycle.
3. On the modelsim command line, run source setup.tcl. This is a small script that automatically compiles the code, generates the simulation (though it doesn't run it), and adds the objects into the wave view. If this doesn't work, then you can just compile and run the normal way.

How the code runs

2 Bit Counter Vhdl

The first clock cycle is always dedicated to reading the code from instructions.txt and saving it into the instruction memory (found in instruction_memory.vhd). It has nothing to do with the processor itself. This is just a preliminary action. Starting on the second clock cycle is when the program runs.

Every clock cycle after the first reads an instruction from the instruction memory and increments the program counter accordingly. The program will continue to run until the pc has reached an address greater than the address of the last instruction in memory. The instruction, data, and register memory will still persist after the program ends and will only change if it is overwritten, or the simulation ends.

Suported Instructions

Instruction	Format	Operation	Syntax
Add	R	R[rd] = R[rs] + R[rt]	add $rd, $rs, $rt
Add immediate	I	R[rt] = R[rs] + immed.	addi $rt, $rs, immed.
And	R	R[rd] = R[rs] & R[rt]	and $rd, $rs, $rt
Branch On Equal	I	if (R[rs]R[rt]) PC=PC+4+BranchAddr	beq $rs, $rt, BranchAddr
Branch On Not Equal	I	if (R[rs]!=R[rt]) PC=PC+4+BranchAddr	bne $rs, $rt, BranchAddr
Jump	J	PC=JumpAddr	j JumpAddr
Or	R	R[rd] = R[rs] R[rt]	or $rd, $rs, $rt
Set Less Than	R	R[rd] = (R[rs] < R[rt]) ? 1 : 0	slt $rd, $rs, $rt

Components

Details of the major parts of the processor.

Program Counter Vhdl Xilinx

• main.vhd
  • The main script that is run. This is what should be selected as the design unit when simulating.
• pc.vhd
  • The program counter for pointing to the next instruction.
• instruction_memory.vhd
  • The block of memory that reads the instructions from a file and saves it into a 128 byte block of memory.
• control.vhd
  • Sets all the flags coming out of the controller appropriately given the 6-bit opcode
• registers.vhd
  • The block of 32 32-bit registers.
• sign_extend.vhd
  • Turns the 16-bit immediate to a 32-bit one by appending zeros. (Doesn't work yet with negative numbers.)
• alu_control.vhd
  • Given the 6-bit opcode and the 6-bit function, this chooses the operation the ALU should perform.
• alu.vhd
  • The ALU that performs either addition, subtraction, and-ing, or-ing, or set-on-less-than operations given the output of the ALU control.
• mux.vhd
  • Simple multiplexer implementation. Can only choose from 2 different inputs for now since 2 are all that's required.
• adder.vhd
  • The only reason why I made this is because the picture had an adder component in it. If the picture had a dragon on it, I would print out an ascii dragon to the wave view.
• shifter.vhd
  • For all your bit shifting needs.
• sign_extend.vhd
  • For ll you sign extending needs. Isn't this a very accurate description.
• memory.vhd
  • Sample text

Todo

Vhdl Counter Code

1. Add lw and sw support.
2. Profit.
3. Ayy lmao.